CPU sub-system cores ACore (Single ARM) MCore (Single MIPS) PROMIPS (Dual MIPS) RTL interface tools VP (VLSI Pilot for EDA tools) VECOOL (VLSI ECO Optimized Language) PT2XL® (PrimeTime to XL converter) SOC Development platforms CATSEYE (Dual MIPS CPU + FPGA) Mixed Signal Cores Serializers / De- serializers Analog Front Ends Services SOC design SOC verification RTL to tape-out STA sign-off
ASICServe  2010

ASIC  STA  VLSI  Home  Contact us